Personal information
Konstantin Bragin
Phone +7 (915) 220-30-25
Location: Russia, Moscow, Zelenograd
Re-location: possible
Date of birth: 09.10.1983
Marital status: married

Work experience
since 02.2011 IDM-PLUS, Russia, Moscow
ASIC Digital Design Engineer

-MCU architecture
-RTL coding
-modelling of individual units
-logic sinthesis (with BSD/DFT)
-specification development
-control over functional verification
-cooperation with application engineers/test engineers/analog engineers/back-end command

— development languages: Verilog/SystemVerilog
— logic synthesis: Synopsys DC
— formal verification: Synopsys Formality
— modelling and functional verification: Cadence Incisive
— version control systems: svn

08.2008 — 02.2011  ELVEES, Russia, Moscow
ASIC Verification Engineer

— development of a test environment
— writing of the test plan
— development of tests
— error trapping in the project and interaction with developers
— rtl code coverage analysis
— regression control of tests
— running and analysis results of tests for gate-model
— development languages and libraries: С++/STL/SystemC/SCV, SystemVerilog/OVM
— CAD: Cadence IUS
— version control systems: cvs, svn
— compilation and building: gcc, make
— bug-tracking and project managment: MS SharePoint, GNU gnats, Mantis, MediaWiki

06.2007 — 07.2008 IPMCE (Institute of Precision Mechanics and Computer Engineering), Russia, Moscow

— development of a layout standart cells, preparation and implementation of a cells characterization
— automation of a development stages (tcl, skill scripts)
— basic skills of VLSI physical design

09.2006 — 11.2007 IPPM RAS (Institute for Design Problems in Microelectronics), Russia, Moscow

— participation in development and testing of the software (generating test sequences for calculation maximum delay of the blocks custom VLSI without preliminary characterization)
— development, improvement of UI
— the analysis of performance
— development languages: C, Tcl&Tk (UI)
— compilation and building: gcc, make

2008 — Moscow Institute of Electronic Technology, Department of Electronics and Computer Technologies/ Master degree in VLSI Design

2008 — VLSI Design through the use of Synopsys EDA tools

Russian — native
English — intermediate

Key skills
— hardware development and verification languages: Verilog/SystemVerilog, SystemC, VHDL
— programming languages С/C++, bash, Tcl&Tk, knowledge of OOP
— verification methodologies: OVM,UVM, using VerificationIP
— interfaces: SPI, I2C, SpaceWire, UART, USB, JTAG, GPIO, MII
— system blocks: FPU, RAM/Flash controllers, timers, AMBA AHB/AXI,
— CAD: Cadence(IUS, Virtuoso, Skill), Synopsys(DC/PT/FM/VCS/Nanochar/Cosmos), Aldec Active-Hdl, Altera Quartus
— project managment systems: MS SharePoint, GNU gnats, Mantis, wiki, Redmine
— version control systems: SVN, CVS
— utilities: gcc, make
— OS: CentOS/Fedora/Red Hat/Suse/Slackware/Ubuntu Linux
— disciplined, inquisitived, communicatived

family, travelling, reading books, web


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